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TranslationMobile

邏輯狀態(tài)

"logical" in Chinese : adj. 1.邏輯的，邏輯上的；邏輯學(xué)上的。 2.合乎邏 ...
"state" in Chinese : n. 1.〔常作 S-〕國，國家；〔通例作 S-〕(美國 ...
"be logical" in Chinese : 合乎邏輯
"logical" in Chinese : adj. 1.邏輯的，邏輯上的；邏輯學(xué)上的。 2.合乎邏輯的。 3.邏輯上必 ...
"logical and" in Chinese : 邏輯與
"logical if" in Chinese : 邏輯若
"logical not" in Chinese : 邏輯非
"logical or" in Chinese : 邏輯或
"logical-in" in Chinese : 邏輯歸入
"the logical" in Chinese : 合選輯之歌
"in a state" in Chinese : 處于糟糕、混亂或不整潔的狀態(tài)
"in a state of" in Chinese : 處于……的狀態(tài)
"in state" in Chinese : 本州的; 正式地, 莊重地
"on state" in Chinese : 導(dǎo)通狀態(tài); 接通的; 通態(tài)
"state" in Chinese : n. 1.〔常作 S-〕國，國家；〔通例作 S-〕(美國、澳洲的)州；〔th ...

Examples

To change a physical or logical state to its opposite
將一種物理狀態(tài)或邏輯狀態(tài)變成它的相反的狀態(tài)。
Flags may have one of two logical states , true or false . programs that use flags as arithmetic operands have an environmental dependency
旗標(biāo)可以有兩個邏輯狀態(tài)之一,真或假.使用旗標(biāo)作為計(jì)算操作的程式有環(huán)境相依性
By exploring the characters of dynamic power supply currents of digital circuits using spice , this paper analyzed the relation between iddt and the switching activities when a circuit changes from one logical state to another
本文通過spice實(shí)驗(yàn)研究數(shù)字電路動態(tài)電流的特性，分析了數(shù)字電路的動態(tài)電流與電路邏輯狀態(tài)轉(zhuǎn)變之間的關(guān)系。
While programs in the java language are theoretically immune from " memory leaks , " there are situations in which objects are not garbage collected even though they are no longer part of the program s logical state
雖然用java語言編寫的程序在理論上是不會出現(xiàn)“內(nèi)存泄漏”的，但是有時對象在不再作為程序的邏輯狀態(tài)的一部分之后仍然不被垃圾收集。
The thesis also introduces the virtual instrument ’ s concept , system architecture , etc . the development of virtual instrument ’ s application software is discussed in detail . it includes virtual instrument software architecture ( visa ) , and virtual instrument ’ s software platforms . the thesis discusses the principle and mechanism of work of the simulation of embedded system . by comparing with the principle of traditional logical analyzer , it draw a conclusion that the virtual logical analyzer will work in synchronous way when it is used for both logical state analyzer and logical time analyzer . the thesis
論文接著探討了嵌入式仿真平臺的原理和工作機(jī)制,通過與傳統(tǒng)邏輯分析儀原理的比較,得出了嵌入式仿真平臺下邏輯分析儀無論是做定時分析,還是做狀態(tài)分析都工作在同步方式下;并重點(diǎn)剖析了探頭原理,采樣定理和毛刺,數(shù)據(jù)的建立和保持時間等邏輯分析儀的重要技術(shù)指標(biāo),得出了虛擬環(huán)境對虛擬邏輯分析儀的功能和各項(xiàng)技術(shù)指標(biāo)的影響,還提出了流水線狀態(tài)表的思想和實(shí)現(xiàn)機(jī)制。
In addition to the normal functional interface of a component , by adding a test interface that exposes the logical states of the component , a tester can dynamically monitor and capture states information and service calling sequence of the component during testing
更進(jìn)一步，在進(jìn)行組件集成測試時，本文提出了組件內(nèi)置測試機(jī)制和一種提高組件可測試性的方法，通過對各交互組件進(jìn)行封裝并擴(kuò)展測試接口，達(dá)到在測試時動態(tài)監(jiān)視和捕捉組件狀態(tài)和服務(wù)調(diào)用序列信息的作用。